The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device which can minimize the occurrence of defects due to a change in the volume of an insulation layer.
In a memory device such as DRAM (dynamic random access memory), bit lines are formed to supply current to junction areas to allow a charge to be stored in capacitors and to transmit a difference in amount of charge between capacitors to sense amplifiers to thereby allow the charge stored in the capacitors to be used as data.
Meanwhile, as semiconductor devices become more highly integrated, the size of a contact hole, which serves as an electrical connection path between top and bottom conductors, gradually decreases. In this situation, a method for forming storage node contacts between the bit lines has been disclosed in the art.
Hereafter, a conventional method for manufacturing a semiconductor device, including processes for forming bit lines and storage node contacts, will be schematically explained.
A conductive layer for bit lines is formed on a semiconductor substrate. A hard mask layer is then formed on the conductive layer for bit lines. The bit lines are formed by sequentially etching the hard mask layer and the conductive layer for bit lines. The conductive layer for bit lines comprises a metal layer and the hard mask layer preferably comprises a nitride layer.
A spacer layer comprising a nitride layer is formed on the resultant semiconductor substrate including the bit lines. The spacer layer is formed to prevent the bit lines and storage node contacts, which are subsequently formed, from being short-circuited.
An insulation layer is deposited on the spacer layer to fill spaces defined between the bit lines. Preferably, the insulation layer is deposited as an HDP (high density plasma) layer or as an SOD (spin-on dielectric) layer. A mask pattern is then formed on the insulation layer to expose storage node contact forming regions between the bit lines. Storage node contact holes are defined by etching the insulation layer using the mask pattern as an etch mask. Storage node contacts are formed by filling a polysilicon layer in the storage node contact holes.
The manufacture of a semiconductor device is completed by sequentially conducting a series of subsequent well-known processes.
However, in the conventional method described above, stress is likely to occur in the bit lines in a subsequent process due to a change in the volume of the insulation layer or due to a difference in thermal expansion coefficients of the insulation layer and the bit lines. In particular, the stress occurs unevenly on both sides of each bit line causing the bit line to lean or collapse.
For example, when the insulation is deposited as an HDP layer, stress is occurs unevenly on both sides of each bit line because the thickness of the insulation layer deposited on the sidewalls of the bit line changes largely depending upon the volume of the space between the bit lines. Accordingly, the bit line leans or collapses. When the insulation layer is deposited as an SOD layer, a volume change largely occurs when conducting an annealing process to bake the SOD layer. Accordingly, stress once again occurs unevenly both sides of each bit line and the leaning or collapsing of the bit line occurs.
Specifically, where leaning or collapsing of the bit lines occurs, when defining the storage node contact holes, the storage node contact holes may not be properly defined on a side opposite to the direction in which the bit lines lean or collapse, or the storage node contacts and the bit lines are likely to come into contact with each other and bridges are likely to be formed in the direction in which the bit lines lean or collapse. Consequently, the reliability of the semiconductor device can be degraded and the manufacturing yield can decrease.
In order to reduce the change in the volume of the insulation layer, such as an SOD layer, a method has been suggested in the art. The method suggests that a silicon layer is formed on the nitride spacer layer formed on the bit lines. In this method, the decrease in the volume of the insulation layer can be partially compensated for since the silicon layer is oxidized and increases in volume when annealing the SOD layer.
Nevertheless, utilizing this method, as design rules for semiconductor devices decrease, it is difficult to secure a silicon layer thickness thick enough to compensate for the decrease in the is volume of the insulation layer since the silicon layer cannot be formed to have a thickness greater than 30˜50 Å. As a result, the change in the insulation layer volume cannot be properly reduced.